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LT3988 1 3988f typical a pplica t ion fea t ures descrip t ion dual 60v monolithic 1a step-down switching regulator the lt ? 3988 is a dual, current mode, step-down, dc/dc converter that accepts two input voltages up to 60v (80v transient), which may be driven from separate supplies or can be cascaded. high efficiency switches are included on the die along with internal boost diodes and loop compensa- tion. both converters are capable of generating 1a outputs, are synchronized to a single oscillator programmable up to 2.5mhz, and run with opposite phases, reducing input ripple current. the switching frequency is set with a single resistor yield- ing a range of 250khz to 2.5mhz, or a clock signal can be applied to the sync pin. the LT3988s high switching frequency allows the use of small inductors and capacitors, resulting in a very small dual output supply. the constant switching frequency, combined with low impedance ce - ramic capacitors, results in low, predictable output ripple. a current mode pwm architecture provides fast transient response with cycle-by-cycle current limiting. diode current sense and thermal shutdown provide additional protection. the LT3988 is available in a 16-lead msop package with an exposed pad for low thermal resistance. efficiency a pplica t ions n wide input range: operation from 4.1v to 60v overvoltage lockout protects circuit through 80v transients n two 1a output switching regulators with internal power switches n short circuit robust n adjustable 250khz to 2.5mhz switching frequency, synchronizable over the full range n integrated boost diodes n integrated loop compensation n anti-phase switching reduces ripple n low shutdown i q (<2a) n uses small inductors and ceramic capacitors n thermally enhanced, 16-lead msop package n commercial vehicle battery regulation n industrial supplies n distributed supply regulation l , lt, ltc, ltm, linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. i out (a) 0 0.2 0.4 0.6 0.8 0.1 0.3 0.5 0.7 0.9 efficiency (%) 1 3988 ta01b v out = 3.3v v in = 12v f sw = 500khz v out = 5v 85 55 60 50 90 65 70 75 80 1000pf 57.6k 34k 22h v in 7v to 60v transient to 80v v out1 5v, 1a v out2 3.3v, 1a 0.22f 47f 3988 ta01 4.7f 10.2k 1000pf 15h 0.22f 47f 10k 22pf fb1 da1 sw1 boost1 sync track/ss1 fb2 da2 sw2 boost2 track/ss2 en/uvlo gnd v in1 v in2 LT3988 200k rt bd
LT3988 2 3988f p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in (notes 7, 8) .......................................... C0 .3v to 80v boost ...................................................................... 8 0v en/uvlo (note 7) ..................................................... 8 0v boost above sw ..................................................... 3 0v en/uvlo above v in1 ................................................... 6v rt, s ync .................................................................... 6v t rack/ss, fb ............................................................ 5v bd ............................................................................. 2 0v operating junction temperature range (note 2) LT3988e ............................................ C4 0c to 125c LT3988i ............................................. C4 0c to 125c LT3988h ............................................ C 40c to 150c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) ................... 3 00c (note 1) 1 2 3 4 5 6 7 8 da1 sw1 boost1 bd en/uvlo boost2 sw2 da2 17 gnd 16 15 14 13 12 11 10 9 v in1 track/ss1 fb1 rt sync fb2 track/ss2 v in2 top view mse package 16-lead plastic msop ja = 40c/w, jc = 10c/w exposed pad (pin 17) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range* LT3988emse#pbf LT3988emse#trpbf 3988 16-lead plastic msop C40c to 125c LT3988imse#pbf LT3988imse#trpbf 3988 16-lead plastic msop C40c to 125c LT3988hmse#pbf LT3988hmse#trpbf 3988 16-lead plastic msop C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in1/2 = 12v, unless otherwise noted. (notes 2, 5, 6) parameter conditions min typ max units v in1 undervoltage lockout (note 3) v in1 rising l 3.9 4.1 v v in1 undervoltage lockout hysteresis 260 mv v in1 overvoltage lockout (note 3) v in1 rising l 60 64 66 v v in1 overvoltage lockout hysteresis 2.1 v v in2 undervoltage lockout (note 3) v in2 rising, v in1 = 4.1v l 2 2.6 3.1 v v in2 undervoltage lockout hysteresis 135 mv en/uvlo input current v en/uvlo = 1.2v C0.5 0.5 a en/uvlo enable threshold 300 500 mv en/uvlo undervoltage threshold v en/uvlo = rising l 1.1 1.2 1.3 v en/uvlo undervoltage threshold hysteresis 120 mv
LT3988 3 3988f e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT3988e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LT3988i is guaranteed over the full C40c to 125c operating junction temperature range. the LT3988h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 3: undervoltage lockout occurs when v in is lower than the undervoltage threshold. overvoltage lockout occurs when v in exceeds the threshold voltage. see applications information. the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v in1 /v in2 = 12v, unless otherwise noted. (notes 2, 5, 6) parameter conditions min typ max units v in1 quiescent current v fb1 = 0.9v, v bd = 0v 2.7 4.5 ma v in1 quiescent current v fb1 = 0.9v, v bd = 5v 1.6 3 ma v in2 quiescent current v fb2 = 0.9v, v bd = 5v 250 1000 a bd pin current v bd = 0v C8 C30 a bd pin quiescent current v bd = 5v 1.1 2.2 ma shutdown current (i vin1 +i vin2 ) v en/uvlo 0.3v 0.1 1 a fb voltage l 0.74 0.735 0.75 0.75 0.76 0.765 v v fb pin bias current v fb = 0.75v l C5 C100 na fb line voltage regulation 5v < v in < 60v 0.01 %/v switching frequency r t = 40.2k l 0.9 1 1.1 mhz switching frequency r t = 200k 250 khz switching frequency r t = 14.7k 2.15 mhz switching phase, sw1 to sw2 r t = 40.2k 150 180 210 deg da comparator current threshold l 1.1 1.32 1.58 a switch v sat i sw = 1a 850 mv switch current limit (note 4) duty cycle = 35% 1.4 1.87 2.25 a switch leakage current 0.01 1 a minimum boost voltage 2 2.5 v boost pin current i sw = 1a 20 50 ma boost diode forward voltage i bd = 50ma 0.7 0.9 v boost diode leakage current v r = 5v 0.1 5 a track/ss pin current v track/ss = 1v C0.8 C1.3 C2.2 a sync input high voltage v ih l 1.5 v sync input low voltage v il l 0.4 v sync input frequency 0.25 2.5 mhz sync pin input current v sync = 1.5v 0.3 a note 4: current limit is guaranteed by design and/or correlation to static test. slope compensation reduces current at higher duty cycles. note 5: polarity specification for all currents into pins is positive. all voltages are referenced to gnd unless otherwise specified. note 6: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating junction temperature when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 7: absolute maximum voltage at v in and en/uvlo is 80v for nonrepetitive 1 second transients, and 60v for continuous operation. note 8: if v in2 is driven above 60v, v in2 must be connected to v in1 .
LT3988 4 3988f typical p er f or m ance c harac t eris t ics feedback voltage vs temperature switch current limit vs temperature switch current limit vs duty cycle switching frequency vs r t switching frequency vs temperature switching frequency foldback efficiency, v out = 2.5v efficiency, v out = 3.3v efficiency, v out = 5v load current (a) 0 0.2 0.4 0.6 0.8 0.1 0.3 0.5 0.7 0.9 efficiency (%) 1.0 3988 g01 v in = 48v v in = 24v v in = 12v 45 60 40 55 50 80 65 70 75 f = 500khz v bd = 3v temperature (c) ?50 feedback voltage (v) 0.760 0.755 0.750 0.745 0.740 0 50 ?25 25 100 3988 g04 150 75 125 r t (k) 0 frequency (mhz) 2.5 2.1 1.7 1.3 0.9 0.5 2.3 1.9 1.5 1.1 0.7 0.3 0.1 80 160 40 120 180 3988 g07 200 60 140 20 100 0 0.2 0.4 0.6 0.8 0.1 0.3 0.5 0.7 0.9 efficiency (%) 1.0 3988 g02 v in = 48v v in = 24v v in = 12v load current (a) 85 55 60 50 90 65 70 75 80 f = 500khz temperature (c) ?50 current limit (a) 2.5 2.0 1.5 1.0 0.5 0 50 ?25 25 100 3988 g05 150 75 125 duty cycle = 35% temperature (c) ?50 frequency change (%) 10 5 0 ?5 ?10 0 50 ?25 25 100 3988 g08 150 75 125 0 0.2 0.4 0.6 0.8 0.1 0.3 0.5 0.7 0.9 efficiency (%) 1.0 3988 g03 v in = 48v v in = 24v v in = 12v load current (a) 85 55 60 50 90 65 70 75 80 f = 500khz duty cycle (%) 0 current limit (a) 2.5 2.0 1.5 1.0 0.5 20 40 60 3988 g06 100 80 typical minimum feedback voltage (v) 0 f/f nom 1.2 0.6 0.4 0.8 1.0 0.2 0.4 0.2 0.6 3988 g09 0.7 0.3 0.1 0.5 t a = 25c, unless otherwise noted.
LT3988 5 3988f typical p er f or m ance c harac t eris t ics boost diode voltage vs boost diode current maximum v in for full frequency vs load current minimum switch on-time vs temperature minimum switch off-time vs temperature undervoltage lockout vs temperature no-load supply current vs input voltage switch voltage drop vs load current boost current vs load current v in (v) 0 i q (ma) 3.5 3.3 3.0 2.8 2.6 3.4 3.2 2.9 2.7 3.1 2.5 20 40 10 30 50 3988 g10 60 15 35 5 25 45 55 0 20 40 60 80 boost diode voltage (v) 100 3988 g13 boost diode current (ma) 0.75 0 1.00 0.25 0.50 temperature (c) ?50 minimum off-time (ns) 350 250 200 150 50 100 300 0 0 50 ?25 25 100 3988 g16 150 75 125 0 0.2 0.4 0.6 0.8 voltage drop (v) 1.0 3988 g11 load current (a) 0.8 0 1.0 0.2 0.4 0.6 0 0.2 0.4 0.6 0.8 v in (v) 1.0 3988 g14 load current (a) 30 0 40 10 20 f = 1mhz temperature (c) ?50 v in uvlo (v) 4 3 1 2 0 0 50 ?25 25 100 3988 g17 150 75 125 v in1 rising v in2 rising v in1 falling v in2 falling 0 0.2 0.4 0.6 0.8 boost current (ma) 1.0 3988 g12 load current (a) 15 0 20 5 10 temperature (c) ?50 minimum on-time (ns) 250 200 150 50 100 0 0 50 ?25 25 100 3988 g15 150 75 125 t a = 25c, unless otherwise noted.
LT3988 6 3988f p in func t ions bd: internal boost diodes are connected between the bd pin and the boost pins. connect bd to a 3v or higher supply, such as v out . boost1, boost2: the boost pins are used to provide drive voltages, higher than the input voltage, to the internal npn power switches. da1, da2: tie the da pin to the anode of the external schottky catch diode. if the da pin current exceeds 1.32a, which could occur in an overload or short-circuit condi - tion, switching is disabled until the da pin current falls below 1.32a. en/uvlo: this pin is used to shut down the LT3988. it can be driven from a logic level, tied directly to the input, or used as an undervoltage lockout by connecting a resistor divider from v in1 . fb1, fb2: the LT3988 regulates each feedback pin to 0.750v. connect the feedback resistor divider taps to these pins. gnd: the exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. the exposed pad must be soldered to the circuit board for proper operation. r t: the rt pin is used to set the internal oscillator fre - quency. tie a resistor from rt to gnd for the desired switching frequency. sync: to synchronize the part to an external frequency, drive the sync pin with a logic-level signal with positive and negative pulse widths of at least 100ns. if the sync function is not used, connect the sync pin to ground. if using sync, minimize coupling to rt and fb2, and add decoupling capacitors as needed up to 22pf. sw1, sw2: the sw pins are the outputs of the internal power switches. connect these pins to the inductors, catch diodes and boost capacitors. track/ss1, track/ss2: the track/ss pins are used to soft-start the two channels, to allow one channel to track the other output, or to allow both channels to track another output. for tracking, tie a resistor divider to this pin from the tracked output. for soft-start, tie a capacitor to this pin. an internal C1.2a soft-start current charges the capacitor to create a voltage ramp at the pin. leave these pins disconnected if unused. v in1 : the v in1 pin supplies current to the LT3988 internal circuitry and to the internal power switch connected to sw1 and must be locally bypassed. v in1 must be greater than 3.9v (typ) for channel 1 or channel 2 to operate. v in2 : the v in2 pin supplies current to the internal power switch connected to sw2 and must be locally bypassed. connect this pin directly to v in1 unless power for channel 2 is coming from a different source. v in2 must be greater than 2.6v (typ) and v in1 must be greater than 3.9v (typ) for channel 2 to operate. if v in2 is driven above 60v, v in2 must be connected to v in1 . typical p er f or m ance c harac t eris t ics v in1 overvoltage lockout vs temperature track/ss pin current vs temperature temperature (c) ?50 v in1 ovlo (v) 65 64 63 62 61 0 50 ?25 25 100 3988 g18 150 75 125 v in1 rising v in1 falling temperature (c) ?50 track/ss pin current (a) 1.42 1.38 1.34 1.26 1.30 1.22 0 50 ?25 25 100 3988 g19 150 75 125
LT3988 7 3988f av boost sw fb out c out r2 c3 l1 d1 bd rt gnd da v in v c sync 3988 bd track/ss 0.75v one of two switching regulators shown r1 c in 0.675v g m sw ctl slave osc slope cl clk master osc thermal shutdown en/uvlo int reg and ref c2 1.2a track/ss i limit clamp b lock diagra m figure 1. block diagram of the LT3988 with associated external components
LT3988 8 3988f o pera t ion the LT3988 is a dual, constant frequency, current mode regulator with internal power switches. operation can be best understood by referring to the block diagram in figure 1. if the en/uvlo pin is pulled low, the LT3988 is shut down and draws minimal current from the input source(s) tied to the v in pins. if the en/uvlo pin exceeds 0.5v (typ), the internal bias circuits turn on, including the internal regulator, reference and master oscillator. the switching regulators will only begin to operate when the en/uvlo pin exceeds 1.2v (typ). the switcher is a current mode regulator. instead of directly modulating the duty cycle of the power switch, the feedback loop controls the peak current in the switch during each cycle. compared to voltage mode control, current mode control improves loop dynamics and provides cycle-by- cycle current limit. an oscillator enables an rs flip flop, turning on the internal power switch. an amplifier and comparator monitor the current flowing between the v in and sw pins, turning the switch off when this current reaches a level determined by the voltage at v c . an error amplifier measures the output voltage through an external resistor divider tied to the fb pin and servos the v c voltage. if the error amplifiers output increases, more current is delivered to the output; if it decreases, less current is delivered. an active clamp on the v c voltage provides a current limit. the switching frequency is set either by the resistance to gnd at the rt pin or by the frequency of the logic-level signal driving the sync pin. a detection circuit monitors for the presence of a sync signal on the pin and switches between the two modes upon detection of a clock applied to the sync pin. use of the sync pin as a frequency input requires the use of an r t resistor as well. this requirement is detailed in the switching frequency section. onboard circuitry generates the appropriate slope compensation ramps and generates the 180 out-of-phase clocks for the two channels. each switcher contains an extra, independent oscillator to perform frequency foldback during overload conditions. this slave oscillator is normally synchronized to the master oscillator. a comparator senses when v fb is less than 50% of its regulated value and switches the regulator from the master oscillator to a slower slave oscillator. v fb is less than 50% of its regulated value during start-up, short-circuit, and overload conditions. frequency foldback helps limit switch current under these conditions. the track/ss pins override the 0.75v reference of the fb pins when the track/ss pins are below 0.75v. this allows either coincident or ratiometric supply tracking on start-up as well as a soft-start capability. the switch drivers operate either from v in or from the boost pin. an external capacitor and internal schottky diode are used to generate a voltage at the boost pin that is higher than the input supply. this allows the driver to obtain a low v ce across the internal bipolar npn power switch for efficient operation. the bd pin serves two purposes. the voltage at bd deter - mines the boost1 and boost2 levels over the v in1 and v in2 supply voltages, and allows the internal circuitry to draw its current from a lower voltage supply than v in1 . this reduces power dissipation and increases efficiency. if the voltage at bd falls below 3v, then quiescent current will flow from v in1 . the overvoltage and undervoltage detection shuts down the LT3988 if the input voltage on v in1 goes above or below thresholds. the overvoltage detector shuts down the regulators when v in1 exceeds 60v. an undervoltage detector monitoring v in1 disables both regulators when v in1 is under 3.7v, an undervoltage detector monitoring v in2 shuts down channel 2 when v in2 is under 2.5v. the higher voltage is required on v in1 to accomodate internal bias circuits. additionally, tying the en/uvlo pin to a volt - age divider from v in1 to ground allows a programmable undervoltage threshold.
LT3988 9 3988f a pplica t ions i n f or m a t ion s tep -d own c onsiderations fb resistor network the output voltage is programmed with a resistor divider (refer to the block diagram) between the output and the fb pin. choose the resistors according to: r1 = r2 v out 750mv ? 1 ? ? ? ? ? ? the parallel combination of r1 and r2 should be 20k or less to minimize bias current errors. the maximum error due to v fb bias current is ?v out = i fb(max) ? r1 input voltage range the minimum operating voltage is determined either by the LT3988s undervoltage lockout or by its maximum duty cycle. the duty cycle is the fraction of time that the internal switch is on and is determined by the input and output voltages: dc = v out + v f v in ? v sw + v f where v f is the forward voltage drop of the catch diode (~0.4v) and v sw is the voltage drop of the internal switch (~0.3v at maximum load). this leads to a minimum input voltage of: v in(min) = v out + v f dc max ? v f + v sw the duty cycle is the fraction of time that the internal switch is on during a clock cycle. the maximum duty cycle is generally given by dc max = 1 C t off(min) ? f. however, unlike most fixed frequency regulators, the LT3988 will not switch off at the end of each clock cycle if there is sufficient voltage across the boost capacitor (c3 in figure?1) to fully saturate the output switch. forced switch-off for a minimum time will only occur at the end of a clock cycle when the boost capacitor needs to be recharged. this operation has the same effect as lowering the clock frequency for a fixed off time, resulting in a higher duty cycle and lower minimum input voltage. the resultant duty cycle depends on the charging times of the boost capacitor and can be approximated by the following equation: dc max = b b + 1 where b is the switch pin current divided by the typical boost current from the boost pin current vs switch cur - rent in the typical performance characteristics section. the maximum operating voltage without pulse-skipping is determined by the minimum duty cycle dc min : v in(ps) = v out + v f dc min ? v f + v sw with dc min = t on(min) ? f. the LT3988 will regulate the output current at input volt - ages greater than v in(ps) . exceeding v in(ps) is safe if the output is in regulation, if the external components have adequate ratings to handle the peak conditions and if the peak inductor current does not exceed 2.3a. a saturating inductor may further reduce performance. for robust operation under fault conditions at input voltages of 40v or greater, use an inductor value of 47h or larger and a clock rate of 1mhz or lower. both the maximum and minimum input voltages are a function of the switching frequency and output voltages. therefore the maximum switching frequency must be set to a value that accommodates all the input and output voltage parameters and must meet both of the following criteria for each channel: f max1 = v out + v f v in(ps) ? v sw + v f ? 1 t on(min) f max2 = 1? v out + v f v in(min) ? v sw + v f ? ? ? ? ? ? ? 1 t off(min) the values of t on(min) and t off(min) are functions of i sw and temperature (see chart in the typical performance character - istics section). worst-case values for switch currents greater than 0.5a are t on(min) = 180ns (for t j > 125c t on(min) = 200ns) and t off(min) = 240ns. f max1 is the frequency at which the minimum duty cycle is exceeded. the regulator will skip on pulses in order to reduce the overall duty cycle
LT3988 10 3988f at frequencies above f max1 . it will continue to regulate but with increased inductor current and increased output ripple. f max2 is the frequency at which the maximum duty cycle is exceeded. if there is sufficient charge on the boost capacitor, the regulator will skip off periods to increase the overall duty cycle at frequencies above f max2 . note that the restriction on the operating input voltage refers to steady-state limits to keep the output in regulation; the circuit will tolerate input voltage transients up to the absolute maximum rating. switching frequency once the upper and lower bounds for the switching frequency are found from the duty cycle requirements, the frequency may be set within those bounds. lower frequencies result in lower switching losses, but require larger inductors and capacitors. the user must decide the best trade-off. the switching frequency is set by a resistor connected from the rt pin to ground, or by forcing a clock signal into the sync pin. the LT3988 applies a voltage across this resistor and uses the current to set the oscillator speed. the r t resistor value for a given switching frequency is given by: r t = 1.31 f 2 + 46.56 f ? 7.322 250khz f 2.5mhz where f is in mhz and r t is in k. the frequency sync signal will support v ih logic levels from 1.5v to 5v cmos or ttl. the duty cycle is not important, but it needs a minimum on time of 100ns and a minimum off time of 100ns. r t should be set to provide a frequency within 25% of the final sync frequency. the slope recovery circuit sets the slope compensation to the appropriate value for the synchronized frequency. choose the inductor value based on the lowest potential switching frequency. inductor selection and maximum output current a good first choice for the inductor value is: l = v out + v f 0.6a ? f where v f is the voltage drop of the catch diode (~0.4v) and f is in mhz. the inductors rms current rating must be greater than the maximum load current and its saturation current table 1. inductors mfg url part series inductance range (h) size (mm) (l w h) coilcraft http://www.coilcraft.com xpl7030 xfl4020 xal50xx 0.13 to 22 1 to 4.7 0.16 to 22 7 7 3 4 4 2.15 5.28 5.48 5.1 cooper http://www.cooperbussmann.com dra74 dr1040 0.33 to 1000 1.5 to 330 7.6 7.6 4.35 10.5 10.3 4 cws http://www.coilws.com sp-0703 sp-0704 sb-1004 3 to 100 2.2 to 100 10 to 1500 7 7 3 7 7 4 10.1 10.1 4.5 murata http://www.murata.com lqh55d lqh6pp lqh88p 0.12 to 10000 1 to 100 1 to 100 5 5.7 4.7 6 6 4.3 8 8 3.8 sumida http://www.sumida.com cdmc6d28 cdeir8d38f 0.2 to 4.7 4 to 22 7.25 6.7 3 8.5 8.3 4 toko http://www.toko.co.jp ds84lcb fdv0620 1 to 100 0.2 to 4.7 8.4 8.3 4 6.7 7.4 2 vishay http://www.vishay.com ihlp-2020ab-11 ihlp-2020bz-11 ihlp-2525cz-11 0.1 to 4.7 0.1 to 10 1 to 22 5.49 5.18 1.2 5.49 5.18 2 6.86 6.47 3 wrth http://www.we-online.de we-pd2-s we-pd-m we-pd2-xl 1 to 68 1 to 1000 10 to 820 4 4.5 3.2 7.3 7.3 4.5 9 10 5.4 a pplica t ions i n f or m a t ion
LT3988 11 3988f should be at least 30% higher. for highest efficiency, the series resistance (dcr) should be less than 0.1. table 1 lists several vendors and types that are suitable. the current in the inductor is a triangle wave with an average value equal to the load current. the peak switch current is equal to the output current plus half the peak-to- peak inductor ripple current. the LT3988 limits its switch current in order to protect itself and the system from overload faults. therefore, the maximum output current that the LT3988 will deliver depends on the switch current limit, the inductor value and the input and output voltages. when the switch is off, the potential across the inductor is the output voltage plus the catch diode drop. this gives the peak-to-peak ripple current in the inductor: ? i l = 1? dc ( ) ? v out + v f l ? f where f is the switching frequency of the LT3988 and l is the value of the inductor. in continuous mode, the peak inductor and switch current is: i swpk = i lpk = ? i l 2 + i l to maintain output regulation, this peak current must be less than the LT3988s switch current limit, i lim . for both switches, i lim is at least 1.5a at low duty cycle and decreases linearly to 1.1a at dc = 90%. (see chart in the typical performance characteristics section). the minimum inductance can now be calculated as: l min = 1? dc min 2 ? f ? v out + v f i lim ? i out however, its generally better to use an inductor larger than the minimum value. the minimum inductor has large ripple currents which increase core losses and require large output capacitors to keep output voltage ripple low. this analysis is valid for continuous mode operation (i out > ?i l /2). for details of maximum output current in discontinu- ous mode operation, see linear technologys application note an44. finally, for duty cycles greater than 50% (v out / v in > 0.5), a minimum inductance is required to avoid subharmonic oscillations. this minimum inductance is: l min = v out + v f 1.25a ? f with l min in h and f in mhz. for robust operation under fault conditions at input volt- ages of 40v or greater, use an inductor value of 47h or larger and a clock rate of 1mhz or lower. output capacitor selection the output capacitor filters the inductor current to generate an output with low voltage ripple. it also stores energy in order to satisfy transient loads and stabilize the LT3988s control loop. because the LT3988 operates at a high frequency, minimal output capacitance is necessary. in addition, the control loop operates well with or without the presence of output capacitor series resistance (esr). ceramic capacitors, which achieve very low output ripple and small circuit size, are therefore an option. you can estimate output ripple with the following equations: v ripple = ? i l 8 ? f ? c out for ceramic capacitors and v ripple = ? i l ? esr for electrolytic capacitors (tantalum and aluminum) where ? i l is the peak-to-peak ripple current in the inductor. the rms content of this ripple is very low so the rms current rating of the output capacitor is usually not of concern. it can be estimated with the formula: i c(rms) = ? i l 12 another constraint on the output capacitor is that it must have greater energy storage than the inductor; if the stored energy in the inductor transfers to the output, the resulting voltage step should be small compared to the regulation voltage. for a 5% overshoot, this requirement indicates: c out > 10 ? l ? i lim v out ? ? ? ? ? ? 2 a pplica t ions i n f or m a t ion
LT3988 12 3988f the low esr and small size of ceramic capacitors make them the preferred type for LT3988 applications. not all ceramic capacitors are the same, however. many of the higher value capacitors use poor dielectrics with high temperature and voltage coefficients. in particular, y5v and z5u types lose a large fraction of their capacitance with applied voltage and at temperature extremes. because loop stability and transient response depend on the value of c out , this loss may be unacceptable. use x7r and x5r types. electrolytic capacitors are also an option. the esrs of most aluminum electrolytic capacitors are too large to deliver low output ripple. tantalum, as well as newer, lower-esr organic electrolytic capacitors intended for power supply use are suitable. choose a capacitor with a low enough esr for the required output ripple. because the volume of the capacitor determines its esr, both the size and the value will be larger than a ceramic capacitor that would give similar ripple performance. one benefit is that the larger capacitance may give better transient response for large changes in load current. table 2 lists several capacitor vendors. table 2. low esr surface mount capacitors mfg type series avx ceramic tantalum tps johansen ceramic x7r, 1812 mlcc kemet tantalum tantalum organic aluminum organic t491,t494,t498 t520,t521,t528 a700 panasonic aluminum organic sp cap sanyo tantalum aluminum organic poscap taiyo-yuden ceramic tdk ceramic diode selection the catch diode (d1 from figure 1) conducts the inductor current during the switch off time. use a schottky diode rated for 1a to 2a average current. peak reverse voltage across the diode is equal to the regulator input voltage. use a diode with a reverse voltage rating greater than the input voltage. the ovlo function of the LT3988 turns off the switch when v in > 64v (typ) allowing use of schottky a pplica t ions i n f or m a t ion diodes with a 70v rating for input voltages up to 80v. table?3 lists several schottky diodes and their manufacturers. table 3. schottky diodes part number v r (v) i avg (a) v f at 1a (mv) v f at 2a (mv) on semiconductor nsr10f40nxt5g 40 1 490 mbra160t3 60 1 510 mbrs190t3 90 1 750 mbrs260t3g 60 2 430 diodes inc b140 40 1 500 b160 60 1 700 b170 70 1 790 b180 80 1 790 b260 60 2 700 b280 80 2 790 dfls140l 40 1 550 dfls160l 60 1 500 dfls260 60 2 620 boost pin considerations the external capacitor and the internal diode tied to the boost pin generate a voltage that is higher than the input voltage. in most cases, a small ceramic capacitor will work well. the capacitor value is a function of the switching frequency, peak current, duty cycle and boost voltage. figure 2 shows three ways to arrange the boost circuit. the boost pin must be more than 2.3v above the sw pin for full efficiency. for outputs of 3.3v and higher, the standard circuit (figure 2a) is best. for lower output voltages, the bd pin can be tied to the input (figure 2b). the circuit in figure 2a is more efficient because the boost pin current comes from a lower voltage source. finally, as shown in figure 2c, the bd pin can be tied to another source that is at least 3v. for example, if you are generating 3.3v and 1.8v and the 3.3v is on whenever the 1.8v is on, the bd pin can be connected to the 3.3v output. (see output voltage tracking). be sure that the maximum voltage at the boost pin is less than 80v and the voltage difference between the boost and sw pins is less than 30v. the minimum operating voltage of an LT3988 application is limited by the internal 4v undervoltage lockout and by the maximum duty cycle.
LT3988 13 3988f a pplica t ions i n f or m a t ion the boost circuit also limits the minimum input voltage for proper start-up. if the input voltage ramps slowly, or the LT3988 turns on when the output is already in regulation, the boost capacitor may not be fully charged. because the boost capacitor charges with the energy stored in the inductor, the circuit will rely on some minimum load current to get the boost circuit running properly. this minimum load will depend on input and output voltages, and on the arrangement of the boost circuit. the minimum load cur - rent generally goes to zero once the circuit has started. figure 4 shows a plot of input voltage to start and to run as a function of load current. even without an output load current, in many cases the discharged output capacitor will present a load to the switcher that will allow it to start. the boost current is generally small but can become sig- nificant at high duty cycles. the required boost current is: i boost = v out v in ? ? ? ? ? ? i out 40 ? ? ? ? ? ? figure 3. diode d4 prevents a shorted input from discharging a backup battery tied to the output figure 4. the minimum input voltage depends on output voltage, load current, and boost circuit figure 2. generating the boost voltage converter with backup output regulator there is another situation to consider: systems where the output will be held high when the input to the LT3988 is absent. if the v in pin is grounded while the output is held high, then diodes inside the LT3988 can pull large currents from the output through the sw and v in pins. a schottky diode in series with the input to the LT3988, as shown in figure 3, will protect the LT3988 and the system from a shorted or reversed input. v in v out v boost ? v sw ? v out max v boost ? v in + v out 3988 f02 c3 v in sw gnd bd boost (2a) v in v out v boost ? v sw ? v in max v boost ? 2v in c3 v in sw gnd bd boost (2b) v in v out v boost ? v sw ? v in3 max v boost ? v in3 + v in min value for v in3 = 3v v in sw gnd bd boost (2c) v in3 > 3v 3988 f03 v in d4 sw gnd v out LT3988 load current (ma) 0 5.0 5.5 800 3988 f04a 4.5 4.0 400 200 600 1000 3.5 input voltage (v) t a = 25c to start to run load current (ma) 0 6.6 7.0 800 3988 f04b 6.2 5.8 400 200 600 1000 5.4 input voltage (v) t a = 25c to start to run minimum input voltage, v out = 3.3v minimum input voltage, v out = 5v
LT3988 14 3988f a pplica t ions i n f or m a t ion input capacitor selection bypass the input of the LT3988 circuit with a 4.7f or higher ceramic capacitor of x7r or x5r type. a lower value or a less expensive y5v type will work if there is additional bypassing provided by bulk electrolytic capacitors, or if the input source impedance is low. the following paragraphs describe the input capacitor considerations in more detail. step-down regulators draw current from the input supply in pulses with very fast rise and fall times. the input ca - pacitor is required to reduce the resulting voltage ripple at the LT3988 input and to force this switching current into a tight local loop, minimizing emi. the input capacitor must have low impedance at the switching frequency to do this effectively and it must have an adequate ripple current rat- ing. with two switchers operating at the same frequency but with different phases and duty cycles, calculating the input capacitor rms current is not simple; however, a conservative value is the rms input current for the phase delivering the most power (v out ? i out ): i in(rms) = i out ? v out v in ? v out ( ) v in < i out 2 and is largest when v in = 2v out (50% duty cycle). as the second, lower power channel draws input current, the input capacitors rms current actually decreases as the out-of-phase current cancels the current drawn by the higher power channel. considering that the maximum load current from a single phase (if sw1 and sw2 are both at maximum current) is ~1a, rms ripple current will always be less than 0.5a. the high frequency of the LT3988 reduces the energy storage requirements of the input capacitor, so that the capacitance required is often less than 10f. the combi - nation of small size and low impedance (low equivalent series resistance or esr) of ceramic capacitors makes them the preferred choice. the low esr results in very low voltage ripple. ceramic capacitors can handle larger magnitudes of ripple current than other capacitor types of the same value. an alternative to a high value ceramic capacitor is a lower value along with a larger electrolytic capacitor, for example a 1f ceramic capacitor in parallel with a low esr tantalum capacitor. for the electrolytic capacitor, a value larger than 10f will be required to meet the esr and ripple current requirements. because the input capacitor is likely to see high surge currents when the input source is applied, tan - talum capacitors should be surge rated. the manufacturer may also recommend operation below the rated voltage of the capacitor. be sure to place the 1f ceramic as close as possible to the v in and gnd pins on the ic for optimal noise immunity. a final caution is in order regarding the use of ceramic capacitors at the input. a ceramic input capacitor can combine with stray inductance to form a resonant tank circuit. if power is applied quickly (for example by plugging the circuit into a live power source), this tank can ring, doubling the input voltage and damaging the LT3988. the solution is to either clamp the input voltage or dampen the tank circuit by adding a lossy capacitor in parallel with the ceramic capacitor. for details, see application note 88. frequency compensation the LT3988 uses current mode control to regulate the output. this simplifies loop compensation. in particular, the LT3988 does not depend on the esr of the output capacitor for stability, so you are free to use ceramic capacitors to achieve low output ripple and small circuit size. the LT3988 is internally compensated with the rc network tied to the vc node. the internal compensation network is optimized to provide stability over the full frequency range. figure 5 shows an equivalent circuit for the LT3988 control loop. the error amplifier is a transconductance amplifier with 0.75v LT3988 3988 f05 r1 out r esr c c 40pf r c 300k v c 7m error amplifier fb r2 c out current mode power stage c pl g m = 2a/v g m = 40a/v figure 5. model for loop response
LT3988 15 3988f output voltage tracking the LT3988 allows the user to program how the output ramps up by means of the track/ss pins. through these pins, either channel output can be set up to either coin- cidently or ratiometrically track the other channel output. this example will show the channel 2 output tracking the channel 1 output, as shown in figure 7. the track/ss2 pin acts as a clamp on channel 2s ref - erence voltage. v out2 is referenced to the track/ss2 voltage when the track/ss2 < 0.8v and to the internal precision reference when track/ss2 > 0.8v. to imple - ment the coincident tracking in figure 7, connect an extra resistive divider to the output of channel 1 and connect its midpoint to the track/ss2 pin (figure 8). the ratio of this divider should be selected to be the same as that of channel 2s feedback divider (r5 = r3 and r6 = r4). in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 6, change the extra divider ratio to r5 = r1 and r6 = r2 + ? r. the extra resistance on r6 should be set so that the track/ss2 voltage is 1v when v out1 is at its final value. the need for this extra resistance is best understood with the help of the equivalent input circuit shown in figure 9. a pplica t ions i n f or m a t ion finite output impedance. the power section, consisting of the modulator, power switch and inductor, is modeled as a transconductance amplifier generating an output current proportional to the voltage at the v c node. note that the output capacitor integrates this current, and that the capacitor on the v c node (c c ) integrates the er - ror amplifier output current, resulting in two poles in the loop. r c provides a zero. with the recommended output capacitor, the loop crossover occurs above the r c c c zero. this simple model works well as long as the value of the inductor is not too high and the loop crossover frequency is much lower than the switching frequency. with a larger ceramic capacitor (very low esr), crossover may be lower and a phase lead capacitor (cpl) across the feedback divider may improve the phase margin and transient response. large electrolytic capacitors may have an esr large enough to create an additional zero, and the phase lead may not be necessary. if the output capacitor is dif - ferent than the recommended capacitor, stability should be checked across all operating conditions, including load current, input voltage and temperature. the lt1375 data sheet contains a more thorough discussion of loop compensation and describes how to test the stability us- ing a transient load. shutdown the en/uvlo pin is used for two purposes, to place the LT3988 in a low current shutdown mode, and to override the internal undervoltage lockout thresholds with a user programmable threshold. when the en/uvlo pin is pulled to under 0.5v (typ), the LT3988 is in shutdown mode and draws less than 1a from the input supply. when the en/uvlo pin is driven above 0.5v (typ) and less than 1.2v (typ), the internal regulator is activated and the oscillators are operating, but the switching operation of both chan- nels remains inhibited. when the ev/uvlo pin is driven above 1.2v (typ), the undervoltage lockout asserted by the en/uvlo function is released, allowing switching opera- tion of both channels. internal undervoltage detectors will still prevent switching operation on channel 1 until v in1 is greater than 3.9v (typ) and on channel 2 until v in2 is greater than 2.6v (typ). the en/uvlo undervoltage lockout has 120mv (typ) of hysteresis. the en/uvlo pin is rated up to 80v and can be connected directly to the input voltage. the en/uvlo pin may be driven by a voltage divider from v in1 , allowing an externally programmable undervoltage lockout to be set above the internal 3.9v threshold. the undervoltage threshold and hysteresis are given by: v uvth = 1.2 1 + r1 r2 ? ? ? ? ? ? ;r1 = r2 v uvth 1.2 ? 1 ? ? ? ? ? ? v uvhy = 0.12 1 + r1 r2 ? ? ? ? ? ? ;r1 = r2 v uvhy 0.12 ? 1 ? ? ? ? ? ? r2 v in1 3988 f06 r1 en/uvlo 1.2v uvlo + ? figure 6. undervoltage lockout circuit
LT3988 16 3988f time coincident tracking v out1 v out2 output voltage time 3988 f07 ratiometric tracking v out1 v out2 output voltage figure 7. two different modes of output voltage tracking a pplica t ions i n f or m a t ion figure 8. setup for coincident and ratiometric tracking figure 9. equivalent input circuit of error amplifier at the input stage of the error amplifier, two common anode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted com- mon mode voltage. the top two current sources are of the same amplitude. in the coincident mode, the track/ss2 voltage is substantially higher than 0.75v at steady state and effectively turns off d1. d2 and d3 will therefore con- duct the same current and offer tight matching between v fb2 and the internal precision 0.75v reference. in the ratiometric mode with r6 = r2, track/ss2 equals 0.75v at steady state. d1 will divert part of the bias current and make v fb2 slightly lower than 0.75v. although this error is minimized by the exponential i-v characteristic of the diodes, it does impose a finite amount of output voltage deviation. further, when channel 1s output experiences dynamic excursions (under load transient, for example), channel 2 will be affected as well. setting r6 to a value that pushes the trk/ss2 voltage to 1v at steady state will eliminate these problems while providing near ratiometric tracking. the example shows channel 2 tracking channel 1, however either channel may be set up to track the other. soft-start if a capacitor is tied from the track/ss pin to ground, then the internal pull-up current will generate a voltage ramp on this pin. this results in a ramp at the output, limiting the inductor current and therefore input current during start-up. a good value for the soft-start capacitor is c out /10,000, where c out is the value of the output capacitor. r5 r1 r6 r2 v out2 r4 r3 to fb1 pin to trk/ss2 pin to fb2 pin v out1 coincident r3 r4 r5 = r6 = ratiometric r1 r1 v out1 /1v ? 1 selecting values for r5 and r6 3988 f08 1.36a ? + i i d1 track/ss 0.75v fb d2 d3 3988 f09 g m r1 r2 = v out1 0.75 ? 1, r3 r4 = v out2 0.75 ? 1
LT3988 17 3988f a pplica t ions i n f or m a t ion independent input voltages v in1 and v in2 are independent and can be powered with different voltages provided v in1 is present when v in2 is present. each supply must be bypassed as close to the v in pins as possible. for applications requiring large inductors due to high v in to v out ratios, a 2-stage step-down ap- proach may reduce inductor size by allowing an increase in frequency. a dual step-down application steps down the input voltage (v in1 ) to the highest output voltage, then uses that voltage to power the other output (v in2 ). v out1 must be able to provide enough current for its output plus figure 11. subtracting the current when the switch is on (11a) from the current when the switch is off (11b) reveals the path of the high frequency switching current (11c). keep this loop small. the voltage on the sw and boost nodes will also be switched; keep these nodes as small as possible. finally, make sure the circuit is shielded with a local ground plane the input current at v in2 when v out2 is at maximum load. figure 10 shows a 12v to 5v, and 1.8v 2-stage converter using this approach. pcb layout for proper operation and minimum emi, care must be taken during printed circuit board (pcb) layout. figure 11 shows the high current paths in the step-down regula- tor cir cuit. note that in the step-down regulators large, switched currents flow in the power switch, the catch diode and the input capacitor. the loop formed by these figure 10. 1mhz, 2-stage step-down 5v and 1.8v outputs 2200pf 57.6k 14k 6.8h v in 12v v out1 v out1 5v, 500ma v out2 1.8v, 500ma 0.22f 10f 3988 f10 10.2k 2200pf 3.3h 0.22f 22f 10k fb1 da1 sw1 boost1 sync track/ss1 fb2 da2 sw2 boost2 bd track/ss2 en/uvlo gnd v in1 v in2 LT3988 40.2k rt 4.7f 4.7f v in sw gnd (11a) v in v sw c1 d1 c2 3988 f11 l1 sw gnd (11c) v in sw gnd (11b) i c1
LT3988 18 3988f 3988 f12 l2 l1 d2 d1 c10 c9 c2 c8 c7 r7 r6 r4 r3 r5 u1 c1 c3 c4 components should be as small as possible. place these components, along with the inductor and output capacitor, on the same side of the circuit board and connect them on that layer. place a local, unbroken ground plane below these components and tie this ground plane to system ground at one location, ideally at the ground terminal of the output capacitor. additionally, keep the sw and boost nodes as small as possible. figure 12 shows an example of proper pcb layout. thermal considerations the die temperature of the LT3988 must be lower than the maximum rating of 125c (150c for the h-grade). this is generally not a concern unless the ambient temperature is above 85c. for higher temperatures, care should be taken in the layout of the circuit to ensure good heat sinking of the LT3988. the maximum load current should be derated as the ambient temperature approaches 125c (150c a pplica t ions i n f or m a t ion figure 12. sample pc board layout for the h-grade). the die temperature is calculated by multiplying the LT3988 power dissipation by the thermal resistance from junction to ambient. power dissipation within the LT3988 can be estimated by calculating the total power loss from an efficiency measurement and subtract- ing the catch diode loss. thermal resistance depends on the layout of the circuit board, but values from 30c/w to 60c/w are typical. related linear technology publications application notes 19, 35, 44, 76 and 88 contain more detailed descriptions and design information for buck regulators and other switching regulators. the lt1375 data sheet has a more extensive discussion of output ripple, loop compensation, and stability testing. design note 318 shows how to generate a dual polarity output supply using a buck regulator.
LT3988 19 3988f typical a pplica t ions 400khz, 5v and 3.3v outputs c2 2200pf r2 57.6k r4 34k l1 22h v out1 5v, 1a v out2 3.3v, 1a c4 0.22f c6 47f 3988 ta02 r3 10.2k c3 2200pf f sw = 400khz c1 to c7: x5r or x7r d1, d2: diodes, inc. b160 l2 15h c5 0.22f d1 d2 c7 47f r5 10k fb1 da1 sw1 boost1 sync track/ss1 fb2 da2 sw2 boost2 bd track/ss2 en/uvlo gnd v in1 v in2 LT3988 r1 118k rt v in 7v to 40v 80v transient c1 4.7f
LT3988 20 3988f typical a pplica t ions 1mhz, wide input range 5v and 1.8v outputs c2 2200pf r2 57.6k r4 14k l1 6.8h v out1 5v, 0.5a v out2 1.8v, 0.5a c4 0.22f c6 22f 3988 ta03 r3 10.2k c3 2200pf f sw = 1mhz c1 to c7: x5r or x7r d1: diodes, inc. b160 d2: diodes, inc. b120 l2 3.3h c5 0.22f d1 d2 c7 22f r5 10k fb1 da1 sw1 boost1 sync track/ss1 fb2 da2 sw2 boost2 bd track/ss2 en/uvlo gnd v in1 v in2 LT3988 r1 40.2k rt v in 7v to 24v 80v transient c1 4.7f 4.7f v out1
LT3988 21 3988f typical a pplica t ions 700khz, 24v and 12v outputs with coincident tracking c3 2200pf r5 309k r7 150k l1 47h v out1 24v, 1a v out2 12v, 1a c4 0.22f c6 10f 3988 ta04 r6 10k f sw = 700khz c1 to c7: x5r or x7r d1, d2: diodes, inc. b160 r4: use 0.25w resistor derate output current at higher ambient temperatures and input voltages to maintain junction temperature below the absolute maximum. l2 22h c5 0.22f d1 d2 c7 10f r8 10k r3 309k r2 10k fb1 da1 sw1 boost1 sync track/ss1 fb2 da2 sw2 boost2 track/ss2 bd en/uvlo gnd v in1 v in2 LT3988 r1 61.9k rt v in1 26v to 60v 80v transient c1 4.7f c2 4.7f v in2 14v to 60v r4 4.7k
LT3988 22 3988f typical a pplica t ions 400khz, 3.3v and 2.5v outputs c2 2200pf r2 34k r4 23.2k l1 10h v out1 3.3v, 1a v out2 2.5v, 1a v out1 c4 0.22f c6 47f 3988 ta05 r3 10k c3 2200pf f sw = 400khz c1 to c7: x5r or x7r d1, d2: diodes, inc. b180 l2 10h c5 0.22f d1 d2 c7 47f r5 10k fb1 da1 sw1 boost1 sync track/ss1 fb2 da2 sw2 boost2 bd track/ss2 en/uvlo gnd v in1 v in2 LT3988 r1 118k rt v in 5.5v to 32v 80v transient c1 4.7f
LT3988 23 3988f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. msop (mse16) 0911 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 16 16151413121110 1 2 3 4 5 6 7 8 9 9 1 8 note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 6. exposed pad dimension does include mold flash. mold flash on e-pad shall not exceed 0.254mm (.010") per side. 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc bottom view of exposed pad option 2.845 0.102 (.112 .004) 2.845 0.102 (.112 .004) 4.039 0.102 (.159 .004) (note 3) 1.651 0.102 (.065 .004) 1.651 0.102 (.065 .004) 0.1016 0.0508 (.004 .002) 3.00 0.102 (.118 .004) (note 4) 0.280 0.076 (.011 .003) ref 4.90 0.152 (.193 .006) detail ?b? detail ?b? corner tail is part of the leadframe feature. for reference only no measurement purpose 0.12 ref 0.35 ref mse package 16-lead plastic msop, exposed die pad (reference ltc dwg # 05-08-1667 rev e) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
LT3988 24 3988f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0412 ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments lt3509 36v with transient protection to 60v, dual 700ma (i out ), 2.2mhz, high efficiency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 1.9ma, i sd = 1a, 3mm w 4mm dfn-14, msop-16e lt3508 36v with transient protection to 40v, dual 1.4a (i out ), 2.5mhz, high efficiency step-down dc/dc converter v in : 3.7v to 36v, v out(min) = 0.8v, i q = 4.6ma, i sd = 1a, 4mm w 4mm qfn-24, tssop-16e lt3980 58v with transient protection to 80v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode ? operation v in : 3.6v to 58v, transient to 80v, v out(min) = 0.79v, i q = 75a, i sd < 1a, 3mm w 4mm dfn-16, msop-16e lt3970 40v, 350ma (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.5a of quiescent current v in : 4.2v to 40v, v out(min) = 1.2v, i q = 2.5a, i sd < 1a, 2mm w 3mm dfn-10, msop-10 lt3990 60v, 350ma (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.5a of quiescent current v in : 4.2v to 60v, v out(min) = 1.2v, i q = 2.5a, i sd < 1a, 3mm w 3mm dfn-10, msop-16e lt3971 38v, 1.2a (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.8a of quiescent current v in : 4.2v to 38v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3991 55v, 1.2a (i out ), 2mhz, high efficiency step-down dc/dc converter with only 2.8a of quiescent current v in : 4.2v to 55v, v out(min) = 1.2v, i q = 2.8a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3507/lt3507a 36v, triple 2.4a,1.4a, and 1.4a (i out ), 2.5mhz, high efficiency step-down dc/dc converter with ldo controller v in : 4v to 36v, v out(min) = 0.8v, i q = 7ma, i sd = 1a, 5mm w 7mm qfn-38 lt3680 36v, 3a, 2.4mhz high efficiency micropower step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 75a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3693 36v, 3a, 2.4mhz high efficiency step-down dc/dc converter v in : 3.6v to 36v, v out(min) = 0.8v, i q = 1.3ma, i sd < 1a, 3mm w 3mm dfn-10, msop-10e lt3480 36v with transient protection to 60v, 2a (i out ), 2.4mhz, high efficiency step-down dc/dc converter with burst mode operation v in : 3.6v to 38v, transient to 60v, v out(min) = 0.78v, i q = 70a, i sd < 1a, 3mm w 3mm dfn-10, msop-10e c2 1000pf r2 57.6k r4 34k l1 15h v out1 5v, 1a v out2 3.3v, 1a c4 0.22f c6 22f 22pf 3988 ta06 r3 10.2k c3 1000pf c1 to c7: x5r or x7r d1, d2: diodes, inc. b180 en/uvlo threshold = 6.02v l2 10h c5 0.22f d1 d2 c7 47f r5 10k fb1 da1 sw1 boost1 sync 500khz clock track/ss1 fb2 da2 sw2 boost2 bd track/ss2 en/uvlo gnd v in1 v in2 LT3988 r1 100k rt v in 7v to 30v 80v transient r6 40.2k r7 10k c1 4.7f 500khz external sync, 5v and 3.3v outputs with 6v uvlo

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